• Home
  • About Us
    • Partners
    • Careers
  • Products
    • Verification IP's
      • MIPI Verification IP's
      • Networking and SOC Verification IP's
      • Automotive And Serial Bus Verification IP's
      • Storage And Video Verification IP's
    • Memory Model's
      • DDR SDRAM Memory Models
      • Low Power Memory Models
      • Graphics Memory Models
      • Flash Memory Models
      • High Bandwidth Memory Models
      • SDRAM Memory Models
      • SRAM Memory Models
      • Non volatile Memory Models
      • DIMM Memory Models
      • Misc Memory Models
      • DFI Verification IP's
    • SimXL - Emulation Models
      • MIPI Synthesizable Transactors
      • Networking and SOC Synthesizable Transactors
      • Automotive And Serial Bus Synthesizable Transactors
      • Storage And Video Synthesizable Transactors
      • DDR SDRAM Memory Synthesizable Transactors
      • Low Power Memory Synthesizable Transactors
      • Graphics Memory Synthesizable Transactors
      • Flash Memory Synthesizable Transactors
      • High Bandwidth Memory Synthesizable Transactors
      • SDRAM Memory Synthesizable Transactors
      • SRAM Memory Synthesizable Transactors
      • DIMM Memory Synthesizable Transactors
      • Misc Memory Synthesizable Transactors
    • Formal Verification IP (Assertion IP)
      • Networking and SOC Assertion IP's
      • DDR SDRAM Memory Assertion IP's
      • Low Power Memory Assertion IP's
      • Graphics Memory Assertion IP's
      • SDRAM Memory Assertion IP's
      • Misc Memory Assertion IP's
      • Serial Assertion IP's
    • Post Silicon Validation IP's
      • MIPI Post Silicon Validation IP's
    • Design IP's
      • MIPI Design IP's
      • Networking and SOC Design IP's
      • DMA Controller Design IP's
      • Automotive Design IP's
      • Serial Bus Design IP's
      • Audio Video Design IP's
      • Memory Controller Design IP's
  • Customers
  • News & Events
  • Support
  • Contact Us
Products

AMBA 4 ACE-Lite Synthesizable VIP

AMBA 4 ACE-Lite Synthesizable VIP

AMBA 4 ACE-Lite Synthesizable VIP provides a smart way to verify the ARM AMBA 4 ACE-Lite component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's AMBA 4 ACE-Lite Synthesizable VIP is fully compliant with standard AMBA 4 ACE-Lite Specification and provides the following features

Features
  • Compliant with the latest ARM AMBA 4 ACE-Lite Protocol Specification.
  • Supports ACE-Lite Master and Slave.
  • Supports all ACE-Lite data and address widths.
  • Supports all protocol transfer types, burst types, burst lengths, burst sizes and response types.
  • Supports constrained randomization of protocol attributes.
  • Separate address, data and response phases. Separate read, write channels.
  • Support for burst-based transactions with only start address issued.
  • Slave and Master support fine grain control of response per address or per transaction.
  • Programmable wait states or delay insertion on different channels.
  • Ability to inject errors during data transfer.
  • Write strobe support to enable sparse data transfer on the write data bus.
  • Narrow transfer support.
  • Unaligned address access support.
  • Ability to issue multiple outstanding transactions.
  • Out of order transaction completion support.
  • Protected accesses with normal/privileged, secure/non-secure and data/instruction.
  • Ability to configure the width of all signals.
  • Support for bus inactivity detection and timeout.
  • Configurable WID signal enable support.
  • Read data interleaving support with programmable interleave depth and programmable interleave size per transaction to allow fixed and variable data interleaving in a transaction.
  • Atomic access support with normal access and exclusive access
  • Longer bursts up to 256 beats.
  • Quality of Service signaling.
  • Multiple region interfaces.
  • User signaling support.
  • Ability to break longer bursts into multiple shorter bursts
  • Supports unmapped region address accesses
  • AWCACHE and ARCACHE Attributes.
  • Low-power Interface support
  • ACE-Lite specific features
    • Supports functionality to verify ACE-Lite.
    • Supports all ACE-Lite transaction types.
    • Support for multiple outstanding ACE-Lite transactions.
    • Supports all write/read responses.
    • Fine grain control of Initiating Master transaction including main memory access.
    • Fine grain control of Interconnect generated main memory access transactions.
    • Barrier transactions
    • Shareable and Non-shareable transactions.
    • Broadcast cache maintenance operations.
  • Programmable Timeout insertion.
  • Rich set of configuration parameters to control ACE-Lite functionality.
  • On-the-fly protocol and data checking.
  • Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
  • Callbacks in Master and Slave for various events.
  • Status counters for various events on bus.
Benefits
  • Compatible with testbench writing using SmartDV VIP's
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms
AMBA 4 ACE-Lite Synthesizable VIP Env

    Note: Only mails from offical mail ID will be processed

    Request Datasheet
    Request Evaluation

    SmartDV's AMBA 4 ACE-Lite Synthesizable env contains following:

  • Synthesizable transactors
  • Complete regression suite containing all the AMBA 4 ACE-Lite Synthesizable testcases
  • Examples showing how to connect various components, and usage of Synthesizable VIP
  • Detailed documentation of all class, task and functions used in verification env
  • Documentation contains User's Guide and Release notes

Give us your feedback

Was this page helpful?
Ask us a question or get help

Talk to Us

Partner with us

Develop Custom VIP's
Partner for design IP's

Send Enquiry

Quick Contact

A value is required.
A value is required.
A value is required.
A value is required.
Copyright © 2020 SmartDV Technologies India Private Limited All rights reserved.