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Products

AMBA 4 ACE-Lite Synthesizable VIP

AMBA 4 ACE-Lite Synthesizable VIP

AMBA 4 ACE-Lite Synthesizable VIP provides a smart way to verify the ARM AMBA 4 ACE-Lite component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's AMBA 4 ACE-Lite Synthesizable VIP is fully compliant with standard AMBA 4 ACE-Lite Specification and provides the following features

Features
  • Compliant with the latest ARM AMBA 4 ACE-Lite Protocol Specification.
  • Supports ACE-Lite Master and Slave.
  • Supports all ACE-Lite data and address widths.
  • Supports all protocol transfer types, burst types, burst lengths, burst sizes and response types.
  • Supports constrained randomization of protocol attributes.
  • Separate address, data and response phases. Separate read, write channels.
  • Support for burst-based transactions with only start address issued.
  • Slave and Master support fine grain control of response per address or per transaction.
  • Programmable wait states or delay insertion on different channels.
  • Ability to inject errors during data transfer.
  • Write strobe support to enable sparse data transfer on the write data bus.
  • Narrow transfer support.
  • Unaligned address access support.
  • Ability to issue multiple outstanding transactions.
  • Out of order transaction completion support.
  • Protected accesses with normal/privileged, secure/non-secure and data/instruction.
  • Ability to configure the width of all signals.
  • Support for bus inactivity detection and timeout.
  • Configurable WID signal enable support.
  • Read data interleaving support with programmable interleave depth and programmable interleave size per transaction to allow fixed and variable data interleaving in a transaction.
  • Atomic access support with normal access and exclusive access
  • Longer bursts up to 256 beats.
  • Quality of Service signaling.
  • Multiple region interfaces.
  • User signaling support.
  • Ability to break longer bursts into multiple shorter bursts
  • Supports unmapped region address accesses
  • AWCACHE and ARCACHE Attributes.
  • Low-power Interface support
  • ACE-Lite specific features
    • Supports functionality to verify ACE-Lite.
    • Supports all ACE-Lite transaction types.
    • Support for multiple outstanding ACE-Lite transactions.
    • Supports all write/read responses.
    • Fine grain control of Initiating Master transaction including main memory access.
    • Fine grain control of Interconnect generated main memory access transactions.
    • Barrier transactions
    • Shareable and Non-shareable transactions.
    • Broadcast cache maintenance operations.
  • Programmable Timeout insertion.
  • Rich set of configuration parameters to control ACE-Lite functionality.
  • On-the-fly protocol and data checking.
  • Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
  • Callbacks in Master and Slave for various events.
  • Status counters for various events on bus.
Benefits
  • Compatible with testbench writing using SmartDV VIP's
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms
AMBA 4 ACE-Lite Synthesizable VIP Env

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    SmartDV's AMBA 4 ACE-Lite Synthesizable env contains following:

  • Synthesizable transactors
  • Complete regression suite containing all the AMBA 4 ACE-Lite Synthesizable testcases
  • Examples showing how to connect various components, and usage of Synthesizable VIP
  • Detailed documentation of all class, task and functions used in verification env
  • Documentation contains User's Guide and Release notes

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