• Home
  • About Us
    • Partners
    • Careers
  • Products
    • Verification IPs
      • MIPI Verification IPs
      • Networking and SOC Verification IPs
      • Automotive And Serial Bus Verification IPs
      • Storage And Video Verification IPs
    • Memory Models
      • DDR SDRAM Memory Models
      • Low Power Memory Models
      • Graphics Memory Models
      • Flash Memory Models
      • High Bandwidth Memory Models
      • SDRAM Memory Models
      • SRAM Memory Models
      • Non volatile Memory Models
      • DIMM Memory Models
      • Misc Memory Models
      • DFI Verification IPs
    • SimXL - Emulation Models
      • MIPI Synthesizable Transactors
      • Networking and SOC Synthesizable Transactors
      • Automotive And Serial Bus Synthesizable Transactors
      • Storage And Video Synthesizable Transactors
      • DDR SDRAM Memory Synthesizable Transactors
      • Low Power Memory Synthesizable Transactors
      • Graphics Memory Synthesizable Transactors
      • Flash Memory Synthesizable Transactors
      • High Bandwidth Memory Synthesizable Transactors
      • SDRAM Memory Synthesizable Transactors
      • SRAM Memory Synthesizable Transactors
      • Non volatile Memory Synthesizable Transactors
      • DIMM Memory Synthesizable Transactors
      • Misc Memory Synthesizable Transactors
      • DFI Synthesizable Transactors
    • Formal Verification IPs (Assertion IP)
      • Networking and SOC Assertion IPs
      • DDR SDRAM Memory Assertion IPs
      • Low Power Memory Assertion IPs
      • Graphics Memory Assertion IPs
      • High Bandwidth Memory Assertion IPs
      • SDRAM Memory Assertion IPs
      • DFI Assertion IPs
      • Serial Assertion IPs
    • Post Silicon Validation IPs
      • MIPI Post Silicon Validation IPs
    • Design IPs
      • DDR Controller Design IPs
      • Ethernet Design IPs
      • Serial Bus Design IPs
      • Audio Video Design IPs
      • MIPI Design IPs
      • Automotive Design IPs
      • Bridge Design IPs
      • DMA Controller Design IPs
      • Flash Controller Design IPs
      • High Speed Design IPs
  • Customers
  • News & Events
  • Support
  • Contact Us
Products

Toggle Flash Memory Model

Toggle Flash Memory Model

Toggle Flash provides an smart way to verify the Toggle Flash host controller or Toggle Flash memory model of a SOC or a ASIC. The SmartDV's Toggle Flash is fully compliant with standard Toggle Flash Specification and provides the following features.

Toggle Flash Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

Toggle Flash Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Features
  • Compliant with Toggle Flash JESD230/ JESD230A/ JESD230B/ JESD230C/ JESD230D specifications.
  • Supports SDR, Synchronous DDR, NV-DDR2 and Toggle-mode DDR data interface.
  • Supports all mandatory and optional commands.
  • Supports 16 bit bus width operations.
  • Supports Read ID commands.
  • Supports Synchronous reset and Reset LUN commands.
  • Supports Multi-plane commands.
  • Supports Write protect pin for multiple function.
  • Supports Data training.
    • Supports DCC training.
    • Supports Read DQ training.
    • Supports Write DQ training.
  • Supports pausing Data Input and Output.
  • Supports Random Data Out commands.
  • Supports Get features and Set features commands.
  • Supports Feature Address Registers.
  • Configurable speed grades for all data interface.
  • Supports copy back programming.
  • Source Synchronous data interface supports Clock Stop feature.
  • Supports dual data bus.
  • Supports Small Data Move command for both Program and Copy back operations.
  • Rich set of configuration parameters to control Toggle Flash functionality.
  • Supports constrained randomization of protocol attributes.
  • On-the-fly protocol and data checking.
  • Protocol checker fully compliant with Toggle Flash Specification with versions JESD230/ JESD230A/ JESD230B/ JESD230C/ JESD230D.
  • Status counters for various events on bus.
  • Callbacks in host, slave and monitor for user processing of data.
  • Toggle Flash Verification IP comes with complete test suite to test every feature of Toggle Flash specification.
  • Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
  • Built in functional coverage analysis.
  • Supports Callbacks, so that user can access the data observed by monitor.
Benefits
  • Faster testbench development and more complete verification of Toggle Flash designs.
  • Easy to use command interface simplifies testbench control and configuration of Host and Slave.
  • Simplifies results analysis.
  • Runs in every major simulation environment.
Toggle Flash Verification Env

    Note: Only mails from offical mail ID will be processed

    Request Datasheet
    Request Evaluation

    SmartDV's Toggle Flash Verification env contains following.

  • Complete regression suite containing all the Toggle Flash testcases.
  • Examples showing how to connect various components, and usage of Host, Slave and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation contains User's Guide and Release notes.

About SmartDV
Partners
Careers
Products
Customers
News & Events

Verification IP
Memory Models
SimXL - Emulation Models
Formal Verification IP (Assertion IP)
Post-Silicon Validation IP
Design IP

info@smart-dv.com

Contact Us
Support
Copyright © SmartDV Technologies India Private Limited All rights reserved.