• Home
  • About Us
    • Partners
    • Careers
  • Products
    • Verification IP's
      • MIPI Verification IP's
      • Networking and SOC Verification IP's
      • Automotive And Serial Bus Verification IP's
      • Storage And Video Verification IP's
    • Memory Model's
      • DDR SDRAM Memory Models
      • Low Power Memory Models
      • Graphics Memory Models
      • Flash Memory Models
      • High Bandwidth Memory Models
      • SDRAM Memory Models
      • SRAM Memory Models
      • Non volatile Memory Models
      • DIMM Memory Models
      • Misc Memory Models
      • DFI Verification IP's
    • SimXL - Emulation Models
      • MIPI Synthesizable Transactors
      • Networking and SOC Synthesizable Transactors
      • Automotive And Serial Bus Synthesizable Transactors
      • Storage And Video Synthesizable Transactors
      • DDR SDRAM Memory Synthesizable Transactors
      • Low Power Memory Synthesizable Transactors
      • Graphics Memory Synthesizable Transactors
      • Flash Memory Synthesizable Transactors
      • High Bandwidth Memory Synthesizable Transactors
      • SDRAM Memory Synthesizable Transactors
      • SRAM Memory Synthesizable Transactors
      • DIMM Memory Synthesizable Transactors
      • Misc Memory Synthesizable Transactors
      • DFI Synthesizable Transactors
    • Formal Verification IP (Assertion IP)
      • Networking and SOC Assertion IP's
      • DDR SDRAM Memory Assertion IP's
      • Low Power Memory Assertion IP's
      • Graphics Memory Assertion IP's
      • SDRAM Memory Assertion IP's
      • DFI Assertion IP's
      • Serial Assertion IP's
    • Post Silicon Validation IP's
      • MIPI Post Silicon Validation IP's
    • Design IP's
      • MIPI Design IP's
      • Networking and SOC Design IP's
      • DMA Controller Design IP's
      • Automotive Design IP's
      • Serial Bus Design IP's
      • Audio Video Design IP's
      • Memory Controller Design IP's
  • Customers
  • News & Events
  • Support
  • Contact Us
Products

LPDDR2 Memory Model

LPDDR2 Memory Model

LPDDR2 Memory Model provides an smart way to verify the LPDDR2 component of a SOC or a ASIC. The SmartDV's LPDDR2 memory model is fully compliant with standard LPDDR2 Specification and provides the following features. Better than Denali Memory Models.

LPDDR2 Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

LPDDR2 Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Features
  • Supports LPDDR2 memory devices from all leading vendors.
  • Supports 100% of LPDDR2 protocol standard JESD209-2E and JESD209-2F.
  • Supports all the LPDDR2 commands as per the specs.
  • Supports up to 32GB device density
  • Supports the following devices.
    • X8
    • X16
    • X32
  • Supports all speed grades as per specification.
  • Quickly validates the implementation of the LPDDR2 standard JESD209-2E and JESD209-2F.
  • Supports for Programmable Write latency and Read latency.
  • Supports for Programmable burst lengths: 4, 8, and 16.
  • Supports for the following Burst Types,
    • Sequential
    • Interleave
  • Checks for following
    • Check-points include power up, initialization and power off rules,
    • State based rules, Active Command rules,
    • Read/Write Command rules etc.
    • All timing violations.
  • Supports for All Mode registers/Control programming.
  • Supports for NVM device.
  • Supports for ZQ/DQ calibration.
  • Supports for Overlay window Enable/Disable.
  • Supports for Write data Mask.
  • Supports for Power Down and Deep Power Down features.
  • Supports for Auto Precharge option for each burst access
  • Supports for input clock stop and frequency change.
  • Supports for full-timing as well as behavioral versions in one model.
  • Supports for all timing delay ranges in one model: min, typical and max.
  • Optional Partial Array Self Refresh and Temperature Compensated Self Refresh
  • Protocol checker fully compliant with LPDDR2 Specification JESD209-2E and JESD209-2F.
  • Constantly monitors LPDDR2 behavior during simulation.
  • Model detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
  • Built in functional coverage analysis.
  • Supports Callbacks, so that user can access the data observed by monitor.
Benefits
  • Faster testbench development and more complete verification of LPDDR2 designs.
  • Easy to use command interface simplifies monitor control and configuration.
  • Simplifies results analysis.
  • Runs in every major simulation environment.
LPDDR2 Verification Env

    Note: Only mails from offical mail ID will be processed

    Request Datasheet
    Request Evaluation

    SmartDV's LPDDR2 Verification env contains following.

  • Complete regression suite containing all the LPDDR2 testcases.
  • Complete UVM/OVM sequence library for LPDDR2 controller.
  • Examples showing how to connect and usage of Model.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Give us your feedback

Was this page helpful?
Ask us a question or get help

Talk to Us

Partner with us

Develop Custom VIP's
Partner for design IP's

Send Enquiry

Quick Contact

A value is required.
A value is required.
A value is required.
A value is required.
Copyright © 2020 SmartDV Technologies India Private Limited All rights reserved.