• Home
  • About Us
    • Partners
    • Careers
  • Products
    • Verification IP's
      • MIPI Verification IP's
      • Networking and SOC Verification IP's
      • Automotive And Serial Bus Verification IP's
      • Storage And Video Verification IP's
    • Memory Model's
      • DDR SDRAM Memory Models
      • Low Power Memory Models
      • Graphics Memory Models
      • Flash Memory Models
      • High Bandwidth Memory Models
      • SDRAM Memory Models
      • SRAM Memory Models
      • Non volatile Memory Models
      • DIMM Memory Models
      • Misc Memory Models
      • DFI Verification IP's
    • SimXL - Emulation Models
      • MIPI Synthesizable Transactors
      • Networking and SOC Synthesizable Transactors
      • Automotive And Serial Bus Synthesizable Transactors
      • Storage And Video Synthesizable Transactors
      • DDR SDRAM Memory Synthesizable Transactors
      • Low Power Memory Synthesizable Transactors
      • Graphics Memory Synthesizable Transactors
      • Flash Memory Synthesizable Transactors
      • High Bandwidth Memory Synthesizable Transactors
      • SDRAM Memory Synthesizable Transactors
      • SRAM Memory Synthesizable Transactors
      • DIMM Memory Synthesizable Transactors
      • Misc Memory Synthesizable Transactors
    • Formal Verification IP (Assertion IP)
      • Networking and SOC Assertion IP's
      • DDR SDRAM Memory Assertion IP's
      • Low Power Memory Assertion IP's
      • Graphics Memory Assertion IP's
      • SDRAM Memory Assertion IP's
      • Misc Memory Assertion IP's
      • Serial Assertion IP's
    • Post Silicon Validation IP's
      • MIPI Post Silicon Validation IP's
    • Design IP's
      • MIPI Design IP's
      • Networking and SOC Design IP's
      • Automotive Design IP's
      • Serial Bus Design IP's
      • Audio Video Memory Design IP's
  • Customers
  • News & Events
  • Support
  • Contact Us
Products

FCRAM Memory Model

FCRAM Memory Model

FCRAM Memory Model provides an smart way to verify the FCRAM component of a SOC or a ASIC. The SmartDV's FCRAM memory model is fully compliant with standard FCRAM Specification and provides the following features. Better than Denali Memory Models.

FCRAM Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

FCRAM Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Features
  • Supports FCRAM memory devices from all leading vendors.
  • Supports 100% of FCRAM protocol standard FCRAM specifications.
  • Supports all the FCRAM commands as per the specs.
  • Supports up to 512MB device density.
  • Supports up to four internal banks.
  • Supports Programmable Write latency.
  • Supports the following burst lengths.
    • 2
    • 4
    • 8
    • 16
  • Supports sequential burst type.
  • Supports burst order.
  • Supports all mode registers programming.
  • Checks for following
    • Check-points include power on, Initialization and power off rules,
    • State based rules, Active Command rules,
    • Read/Write Command rules etc.
    • All timing violations.
  • Supports for Self Refresh, Power down and deep power down operation.
  • Supports for Auto refresh operation.
  • Supports Additional RDQS Toggle (ART).
  • Supports write data mask and data strobe features.
  • Supports Background refresh and burst terminate operations.
  • Supports Clock Stop Capability during idle periods.
  • Supports all types of timing and protocol violation detection.
  • Constantly monitors FCRAM behavior during simulation.
  • Protocol Checker fully compliant with FCRAM Specification.
  • Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
  • Built in functional coverage analysis.
  • Supports Callbacks, so that user can access the data observed by monitor.
Benefits
  • Faster testbench development and more complete verification of FCRAM designs.
  • Easy to use command interface simplifies monitor control and configuration.
  • Simplifies results analysis.
  • Runs in every major simulation environment.
FCRAM Verification Env

    Note: Only mails from offical mail ID will be processed

    Request Datasheet
    Request Evaluation

    SmartDV's FCRAM Verification env contains following.

  • Complete regression suite containing all the FCRAM testcases.
  • Examples showing how to connect and usage of Model.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Give us your feedback

Was this page helpful?
Ask us a question or get help

Talk to Us

Partner with us

Develop Custom VIP's
Partner for design IP's

Send Enquiry

Quick Contact

A value is required.
A value is required.
A value is required.span>
A value is required.
Copyright © 2019 SmartDV Technologies India Private Limited All rights reserved.