• Home
  • About Us
    • Partners
    • Careers
  • Products
    • Verification IP's
      • MIPI Verification IP's
      • Networking and SOC Verification IP's
      • Automotive And Serial Bus Verification IP's
      • Storage And Video Verification IP's
    • Memory Model's
      • DDR SDRAM Memory Models
      • Low Power Memory Models
      • Graphics Memory Models
      • Flash Memory Models
      • High Bandwidth Memory Models
      • SDRAM Memory Models
      • SRAM Memory Models
      • Non volatile Memory Models
      • DIMM Memory Models
      • Misc Memory Models
      • DFI Verification IP's
    • SimXL - Emulation Models
      • MIPI Synthesizable Transactors
      • Networking and SOC Synthesizable Transactors
      • Automotive And Serial Bus Synthesizable Transactors
      • Storage And Video Synthesizable Transactors
      • DDR SDRAM Memory Synthesizable Transactors
      • Low Power Memory Synthesizable Transactors
      • Graphics Memory Synthesizable Transactors
      • Flash Memory Synthesizable Transactors
      • High Bandwidth Memory Synthesizable Transactors
      • SDRAM Memory Synthesizable Transactors
      • SRAM Memory Synthesizable Transactors
      • DIMM Memory Synthesizable Transactors
      • Misc Memory Synthesizable Transactors
    • Formal Verification IP (Assertion IP)
      • Networking and SOC Assertion IP's
      • DDR SDRAM Memory Assertion IP's
      • Low Power Memory Assertion IP's
      • Graphics Memory Assertion IP's
      • SDRAM Memory Assertion IP's
      • Misc Memory Assertion IP's
      • Serial Assertion IP's
    • Post Silicon Validation IP's
      • MIPI Post Silicon Validation IP's
    • Design IP's
      • MIPI Design IP's
      • Networking and SOC Design IP's
      • Automotive Design IP's
      • Serial Bus Design IP's
      • Audio Video Memory Design IP's
  • Customers
  • News & Events
  • Support
  • Contact Us
Products

MIPI DSI-2 TRANSMITTER IIP

MIPI DSI-2 TRANSMITTER IIP

MIPI DSI-2 Transmitter interface provides full support for the two-wire MIPI DSI-2 Transmitter synchronous serial interface, compatible with MIPI DSI and MIPI DSI 2 Specification version 1.0. Through its MIPI DSI-2 Transmitter compatibility, it provides a simple interface to a wide range of low-cost devices. MIPI DSI-2 Transmitter IIP is proven in FPGA environment.The host interface of the MIPI DSI-2 Transmitter can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

MIPI DSI-2 TRANSMITTER IIP is supported natively in Verilog and VHDL

Features
  • Compliant with MIPI DSI-2 Specification v1.3
  • Compliant with Display Serial Interface (DPI -2) v2.0
  • Supports fully MIPI DSI2 Transmitter functionality
  • Compliant with Display Bus Interface (DBI) v2.0
  • Compliant with Display Command Set (DCS) v1.3
  • Compliant with D - PHY specification v1.1,v1.2,v2.0,v2.1
  • Full MIPI DSI-2 Receiver functionality supporting CPHY and DPHY
  • Supports PPI interface.
  • Supports all types of short and long packets
  • Supports 1 to 4 lane configuration
  • Supports all virtual channel identifier
  • Supports both video and command modes
  • Supports Multiple packets per transmission
  • Supports 1-bit Error Correction and 2 bit Error Detection using ECC (6bit) for Packet header
  • Supports Error Detection techniques for active data using Checksum(16 bit)
  • Interrupt support for indicating internal status and error information
  • Supports sync event payloads
  • Supports Data Interleaving
  • Supports display stream compression (DSC)
  • Supports generic read / write over DBI Interface
  • Supports burst and non burst mode transfer over DPI Interface
  • Supports all BTA (Bi directional Turn around) with contention and fault recovery
  • Supports EOT Enable/ Disable Mechanism
  • Supports Link Merging Function
  • Supports both High speed and Low power packet reception
  • Supports following formats
    • YCbCr Data type
    • RGB Data type
    • YUV Data type
    • RAW Data type
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to microprocessor/microcontroller devices
Benefits
  • Single Site license option is provided to companies designing in a single site.
  • Multi Sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
Deliverables

    Note: Only mails from offical mail ID will be processed

    Request Datasheet
    Request Evaluation

    SmartDV's MIPI DSI-2 Transmitter IP contains following

  • The MIPI DSI-2 Transmitter interface is available in Source and netlist products.
  • The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
  • Easy to use Verilog Test Environment with Verilog Testcases
  • Lint, CDC, Synthesis, Simulation Scripts with waiver files
  • IP-XACT RDL generated address map
  • Firmware code and Linux driver package
  • Documentation contains User's Guide and Release notes.

Give us your feedback

Was this page helpful?
Ask us a question or get help

Talk to Us

Partner with us

Develop Custom VIP's
Partner for design IP's

Send Enquiry

Quick Contact

A value is required.
A value is required.
A value is required.span>
A value is required.
Copyright © 2019 SmartDV Technologies India Private Limited All rights reserved.