MIPI DSI-2 Transmitter interface provides full support for the two-wire MIPI DSI-2 Transmitter synchronous serial interface, compatible with MIPI DSI and MIPI DSI 2 Specification version 1.0. Through its MIPI DSI-2 Transmitter compatibility, it provides a simple interface to a wide range of low-cost devices. MIPI DSI-2 Transmitter IIP is proven in FPGA environment. The host interface of the MIPI DSI-2 Transmitter can be simple interface or can be AMBA APB, AMBA AHB, AMBA AHB-Lite, AMBA AXI, AMBA AXI-Lite, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
MIPI DSI-2 Transmitter IIP is supported natively in Verilog and VHDL
- Features
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- Compliant with MIPI DSI-2 Specification v1.3
- Compliant with Display Serial Interface (DPI -2) v2.0
- Supports fully MIPI DSI2 Transmitter functionality
- Compliant with Display Bus Interface (DBI) v2.0
- Compliant with Display Command Set (DCS) v1.3
- Compliant with D - PHY specification v1.1,v1.2,v2.0,v2.1
- Full MIPI DSI-2 Receiver functionality supporting CPHY and DPHY
- Supports PPI interface.
- Supports all types of short and long packets
- Supports 1 to 4 lane configuration
- Supports all virtual channel identifier
- Supports both video and command modes
- Supports Multiple packets per transmission
- Supports 1-bit Error Correction and 2 bit Error Detection using ECC (6bit) for Packet header
- Supports Error Detection techniques for active data using Checksum(16 bit)
- Interrupt support for indicating internal status and error information
- Supports sync event payloads
- Supports Data Interleaving
- Supports display stream compression (DSC)
- Supports generic read / write over DBI Interface
- Supports burst and non burst mode transfer over DPI Interface
- Supports all BTA (Bi directional Turn around) with contention and fault recovery
- Supports EOT Enable/ Disable Mechanism
- Supports Link Merging Function
- Supports both High speed and Low power packet reception
- Supports following formats
- YCbCr Data type
- RGB Data type
- YUV Data type
- RAW Data type
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Simple interface allows easy connection to microprocessor/microcontroller devices
- Benefits
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- Single Site license option is provided to companies designing in a single site.
- Multi Sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- Deliverables
-
SmartDV's MIPI DSI-2 Transmitter IP contains following
- The MIPI DSI-2 Transmitter interface is available in Source and netlist products.
- The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases
- Lint, CDC, Synthesis, Simulation Scripts with waiver files
- IP-XACT RDL generated address map
- Firmware code and Linux driver package
- Documentation contains User's Guide and Release notes.
