MIPI DSI-2 Transmitter interface provides full support for the two-wire MIPI DSI-2 Transmitter synchronous serial interface, compatible with MIPI DSI and MIPI DSI 2 Specification version 1.0. Through its MIPI DSI-2 Transmitter compatibility, it provides a simple interface to a wide range of low-cost devices. MIPI DSI-2 Transmitter IIP is proven in FPGA environment.The host interface of the MIPI DSI-2 Transmitter can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
MIPI DSI-2 TRANSMITTER IIP is supported natively in Verilog and VHDL
- Features
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- Compliant with MIPI DSI-2 Specification v1.0
- Compliant with Display Serial Interface (DPI -2) v2.00
- Compliant with Display Bus Interface (DBI) v2.00
- Compliant with Display Command Set (DCS) v1.3
- Compliant with C- PHY Specification v0.7 , v1.2
- Compliant with D - PHY specification v1.1,v1.2,v2.0,v2.1
- Full MIPI DSI-2 Transmitter core functionality where D - PHY / C - PHY can be connected
- Supports Data rate in range of 80 Mbps to 2.5Gbps
- Supports PPI interface.
- Supports all types of short packets and long packets
- Supports 1 to 4 lane configurations.
- Supports all virtual channel identifier.
- Supports bus turnaround with contention and fault recovery
- Supports EOT enable/disable mechanism
- Supports switching between Low Power and Ultra Low Power modes (ULPS)
- Supports data interleaving
- Support for generic read/write over DBI Interface
- Supports 8/9/16 bit data transfer in DBI Interface
- Supports burst and non burst mode transfer over DPI Interface
- Supports error detection techniques for active data using checksum (16 bit).
- Supports the following pixel formats
- RGB data type
- 12 bit RGB 444 format
- 24 bit RGB 888 format
- 16 bit RGB 565 format
- 18 bit RGB 666 format
- YCbCr data type
- 20 bit YCbCr 4:2:2
- 24 bit YCbCr 4:2:2
- 16bit YCbCr 4:2:2
- 12 bit YCbCr 4:2:0
- Interrupt support for indicating internal status/error information.
- Fully synthesizable.
- Static synchronous design.
- Positive edge clocking and no internal tri-states.
- Scan test ready.
- Simple interface allows easy connection to microprocessor/microcontroller devices.
- Benefits
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- Single Site license option is provided to companies designing in a single site.
- Multi Sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- Deliverables
-
SmartDV's MIPI DSI-2 Transmitter IP contains following
- The MIPI DSI-2 Transmitter interface is available in Source and netlist products.
- The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases
- Lint, CDC, Synthesis, Simulation Scripts with waiver files
- IP-XACT RDL generated address map
- Firmware code and Linux driver package
- Documentation contains User's Guide and Release notes.
