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DDR4 Assertion IP

DDR4 Assertion IP

DDR4 Assertion IP provides an efficient and smart way to verify the DDR4 designs quickly without a testbench. The SmartDV's DDR4 Assertion IP is fully compliant with standard DDR4 Specification.

DDR4 Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

DDR4 Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Features
  • Specification Compliance
    • Supports DDR4 memory devices from all leading vendors.
    • Supports 100% of DDR4 protocol standard JESD79-4/JESD79-4A/JESD79-4A_r2 and JESD79-4B_draft.pdf.
    • Supports all the DDR4 commands as per the specs.
    • Supports for following Package Pin out and Addressing,
    • 2GB
    • 4GB
    • 8GB
    • 16GB
    • Supports the following devices.
    • X4
    • X8
    • X16
    • Supports all speed grades as per specification.
    • Quickly validates the implementation of the DDR4 standard JESD79-4/JESD79-4A/JESD79-4A_r2 and JESD79-4B_draft.pdf.
    • Supports Programmable Write latency and Read latency.
    • Supports Programmable burst lengths: 4,8.
    • Supports the following burst types.
    • Sequential
    • Interleave
    • Supports burst order.
    • Checks for following
    • Check-points include power up,initialization and power off rules,
    • State based rules, Active Command rules,
    • Read/Write Command rules etc.
    • All timing violations.
    • Supports for all Mode registers programming.
    • Supports for Data Mask and Data Bus Inversion(DBI).
    • Supports for write Leveling for calibrations.
    • Supports for Fine Granularity Refresh Mode.
    • Supports for ZQ Calibration commands.
    • Supports for DQ Vref training
    • Supports for CRC for Write Operations.
    • Supports for DLL features.
    • Supports for Multi purpose Register.
    • Supports for Per Dram Addressability.
    • Supports for CAL Mode Operation.
    • Supports for Command Address Parity features.
    • Supports for Control Gear down mode.
    • Supports for Maximum Power Saving mode.
    • Supports for both Synchronous and Asynchronous On-Die Termination modes.
    • Supports for Power Down features.
    • Supports for input clock stop and frequency change.
    • Supports for full-timing as well as behavioral versions in one model.
    • Supports for all timing delay ranges in one model: min, typical and max.
    • Constantly monitors DDR4 behavior during simulation.
    • Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
  • Assertion IP features
    • Assertion IP includes:
    • System Verilog assertions
    • System Verilog assumptions
    • System Verilog cover properties
    • Synthesizable Verilog Auxiliary code
    • Support Master mode, Slave mode, Monitor mode and Constraint mode.
    • Supports Simulation mode (stimulus from SmartDV DDR4 VIP) and Formal mode (stimulus from Formal tool).
    • Rich set of parameters to configure DDR4 Assertion IP functionality.
Benefits
  • Runs in every major formal and simulation environment.
DDR4 Assertion Env

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    SmartDV's DDR4 Assertion env contains following.

  • Detailed documentation of Assertion IP usage.
  • Documentation also contains User's Guide and Release notes.

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