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AMBA ACE AIP

AMBA ACE AIP

AMBA 4 ACE Assertion IP provides an smart way to verify the ARM AMBA 4 ACE component of a SOC or a ASIC. The SmartDV's AMBA 4 ACE Assertion IP is fully compliant with standard AMBA 4 ACE Specification and provides the following features.

AMBA ACE AIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

AMBA ACE AIP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Features
  • Specification Compliance
    • Compliant with the latest ARM AMBA ACE Protocol Specification.
    • Supports all ACE data and address widths.
    • Supports all protocol transfer types, burst types, burst lengths, burst sizes and response types.
    • Separate address, data and response phases. Separate read, write and snoop channels.
    • Support for burst-based transactions with only start address issued.
    • Write strobe support.
    • Narrow transfer support.
    • Unaligned address access support.
    • Ability to issue multiple outstanding transactions.
    • Out of order transaction completion support.
    • Protected accesses with normal/privileged,secure/non-secure and data/instruction.
    • Ability to configure the width of all signals.
    • Support for bus inactivity detection and timeout.
    • Configurable WID signal enable support.
    • Read data interleaving support with programmable interleave depth and programmable interleave size per transaction to allow fixed and variable data interleaving in a transaction.
    • Atomic access support with normal access and exclusive access.
    • Longer bursts up to 256 beats.
    • Quality of Service signaling.
    • Multiple region interfaces.
    • User signaling support.
    • Ability to break longer bursts into multiple shorter bursts.
    • Supports unmapped region address accesses.
    • AWCACHE and ARCACHE Attributes.
    • ACE specific features
    • Supports functionality to verify ACE and Cache Coherent Interconnect functionality for cache.
    • Supports all ACE transaction types including Snoop, Evict, WriteEvict, Barrier and Distributed virtual memory (DVM) transactions.
    • Support for multiple outstanding ACE transactions.
    • Supports all write/read responses and snoop responses.
    • Support for cache model and snoop filtering
  • Assertion IP features
    • AIP includes:
    • System Verilog assertions
    • System Verilog assumptions
    • System Verilog cover properties
    • Synthesizable Verilog Auxiliary code
    • Support Master mode, Slave mode, Monitor mode and Constraint mode.
    • Supports Simulation mode (stimulus from SmartDV ACE VIP) and Formal mode (stimulus from Formal tool).
    • Rich set of parameters to configure ACE AIP functionality.
Benefits
  • Runs in every major formal and simulation environment.
AMBA ACE Assertion Env

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    SmartDV's AMBA ACE Assertion env contains following.

  • Detailed documentation of AIP usage.
  • Documentation also contains User's Guide and Release notes.

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